FET with gate spacer
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United States of America Patent
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Oct 6, 1992
Grant Date -
N/A
app pub date -
Oct 17, 1989
filing date -
Oct 17, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adajcent double or triple-layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
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