Layout of large multistage interconnection networks technical field
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United States of America Patent
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-
Oct 6, 1992
Grant Date -
N/A
app pub date -
Apr 1, 1988
filing date -
Apr 1, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A technique for laying out large multistage interconnection networks. The invention provides for the division of a network into sub-networks which may be maintained on printed circuit boards and then provides for the addition of switching circuitry at the inputs or outputs of such boards such that pin locations on the boards may be swapped with each other to allow for a parallel interconnection of corresponding pins between the boards. Such parallel interconnection eliminates the existence of rat's nests in the wiring harness.
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