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Abstract

A logic simulator has a time loop with a number of time slots into which events are scheduled. The events are wrapped around the loop, so that event times corresponding to different cycles around the loop may be simultaneously present on the loop. This allows a small loop size to be used, which improves performance. Preferably, the loop size is a prime number. If a complete cycle of the loop is made without finding any non-empty slots a jump is made to the next event time, so as to speed up the processing. In one described embodiment, the loop size is static, while in a second described embodiment the loop size is dynamically varied to minimize the insertion of events with different event times into the same slot.

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First Claim