Process cell for an N-dimensional processor array having a single input element with 2N data inputs, memory, and full function arithmetic logic unit
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United States of America Patent
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Oct 20, 1992
Grant Date -
N/A
app pub date -
May 29, 1990
filing date -
May 29, 1990
priority date (Note) -
Expired
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Abstract
A multi-dimensional processor cell and processor array with massively parallel input/output includes a processor array having a plurality of processor cells interconnected to form an N-dimensional array. The system includes a first group of processor cells having 2N dimensionally adjacent processor cells. At least one input/output device is connected to a surplus data signal port of a second group of processor cells each having fewer than 2N dimensionally adjacent processor cells, for providing massively parallel input/output between the multi-dimensional processor array and the input/output device. The processor system also includes a front end processor for providing processor array instructions in response to application programs running on the front end processor. A processor cell controller, responsive to the processor array commands, broadcasts a sequence of processor cell instructions to all of the processor cells of the multi-dimensional processor array.
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