Importance

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Abstract

A scan line doubler includes an input for receiving a video signal at a first scan rate, an output for providing a video signal at a second scan rate twice the first scan rate, a main path leading between the input and the output. The main path includes a scan line interpolation circuit for averaging pixels over two adjacent lines, a two-to-one scan line compression circuit for compressing original and interpolation scan lines into a scan line doubled format, and an optional additive path insertion location between the line interpolation circuit and the two-to-one line compression circuit. An openable connection path bridging the optional additive path insertion location is replaceable with an additive signal processing path including a field delayed pixel extraction circuit, a control circuit for generating a control in relation to detection of motion within the main path video signal, and a combining circuit responsive to the control for adding to the main path the one field delayed pixels and subtracting the line interpolated pixels, whereby when the optional path is connected, the scan line doubler operates in the horizontal, vertical and temporal domain, and when the optional path is not connected, the scan line doubler operates in the horizontal and vertical domains. An improved and simplified three-dimensional scan line doubler is an aspect of the present invention.

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First Claim