Insulated gate field-effect transistor with gate-drain overlap and method of making the same

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United States of America Patent

PATENT NO 5162884
SERIAL NO

07676083

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Abstract

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A method of forming an insulated-gate field-effect transistor, and the transistor formed thereby, is described. According to a first embodiment, an inverted-T gate structure is formed by the deposition of a polycrystalline silicon layer, followed by the deposition of a metal silicide layer thereover. The metal silicide layer is etched with etchant which does not significantly etch polysilicon, to define the upper portion of the gate electrode. The reachthrough lightly-doped source/drain extensions are then implanted through the polysilicon layer, using the upper gate electrode portion as a mask. Sidewall spacers are formed on the sides of the upper portion of the gate electrode, and the polysilicon etched using the spacers as a mask, to define the inverted-T gate structure. In addition, either with the inverted-T gate structure or in conjunction with conventional gate structures, a method is disclosed which uses a first sidewall film to define the location of the source/drain implant relative to the LDD regions, and a second sidewall spacer to space direct react silicide formation from the gate, so that the dimensions of the graded junction may be defined independently from that of the silicidation reaction.

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Patent Owner(s)

Patent OwnerAddress
SGS-THOMSON MICROELECTRONICS INC A CORP OF DE1310 ELECTONICS DRIVE CARROLLTON TX 75006

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bryant, Frank F Denton, TX 1 73
Liou, Fu-Tai Carrollton, TX 79 1368

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