Importance

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Abstract

A synchronous digital decoding circuit decodes Manchester-encoded data using a clock regenerating circuit which produces a decoding clock that is continuously adjusted in accordance with detected phase deviations in the received data signal. The Manchester-encoded data are transmitted with high-to-low and low-to-high transitions at the centers of the data bit cells. On the receiving end, a digital state machine, which is coupled to a timer/counter unit, detects whether a transition is on-time, early, or late in each bit cell as compared with the established decoding clock. If the transition is early or late, the state machine produces a correction signal which is used to correspondingly shorten or lengthen the clock count by a predetermined incremental amount. The adjustment of the clock counts on an on-going basis reduces or eliminates the phase deviation and prevents the accumulation of phase error over an extended length of time. In the preferred embodiment, an oscillator input of 1.2 MHz is provided to a Mod 12 counter having its output coupled to a Mod 10 counter. The 100 KHz output of the Mod 12 counter is provided to the Mod 10 counter, and the Mod 10 counter normally counts out at 10 clock units (120 oscillator pulses) per bit cell, in order to generate a decoding clock of 10 KHz frequency for a data rate of 10K bits/sec. The incremental time adjustment is preferably in the range of 1-6 oscillator pulses out of 120 oscillator pulses for a bit cell. The original NRZ data can then be recovered by using the adjusted regenerated clock.

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First Claim