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Abstract

A memory device utilized for an image display apparatus, such as a dual port memory. The memory device provides a serial port for performing a serial-access with a display controller and a random port for performing a random-access with a CPU. Such memory device includes memory cell arrays of M rows and N columns, one couple of data registers and pointers. The data stored in one row within the memory cell arrays are divided into data of K columns and another data of N-K columns. When the display controller performs the serial-access, one of the above two data registers can be alternatively used for serially inputting or outputting the data while the another data are transferred between the memory cell arrays and another data register. Or the data can be transferred between the memory cell arrays and both of two data registers. In this case, the serial input or output positions for determining the start addresses are assigned by the pointers. The data are read from or written into the data registers from the start addresses.

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First Claim