Process for forming planarized, air-bridge interconnects on a semiconductor substrate
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United States of America Patent
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Dec 15, 1992
Issued Date -
N/A
app pub date -
Jan 28, 1991
filing date -
Jan 10, 1990
priority date (Note) -
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Abstract
A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.
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