Method for testing mixed scan and non-scan circuitry
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United States of America Patent
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Dec 15, 1992
Grant Date -
N/A
app pub date -
Sep 7, 1990
filing date -
Sep 7, 1990
priority date (Note) -
Expired
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Abstract
A method of performing in-circuit testing of interior points of circuit boards containing both boundary-scan and non-scan components that utilizes the boundary-scan facility. The testing procedure involves isolation of the non-scan components and either driving or sensing voltages at physically accessible test sites. The method permits use of isolation and multiplexing solutions that are ordinarily developed for in-circuit testing of board components, resulting in efficient design and implementation of interconnect tests.
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