Demultiplexer including a three-state gate
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United States of America Patent
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Dec 29, 1992
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N/A
app pub date -
Feb 14, 1991
filing date -
Feb 14, 1991
priority date (Note) -
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Abstract
A demultiplexer includes a plurality of transistors having conduction paths connected between an input terminal and output nodes. The control electrode of every transistor is connected to one line of a most significant bit bus by a first capacitive device, the control electrode of every transistor is also coupled to one line of a least significant bit bus by a second capacitive device. When the capacitive devices associated with the same transistor simultaneously receive an enable signal the transistor is turned on and current flows from the input terminal to an output node. Each transistor within the demultiplexer thus acts as a three state gate.
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