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Abstract

A computer system having two processors (22, 24) with the capability of recovering program execution after a power supply interruption. The processors execute identical programs having executable segments. Control means (26) uses storage registers (38) to write segment initial instruction addresses into the trailing processor's program counter (34) so as to cause the processors to execute in adjacent segments. The control means also uses program wait loops to cause the processors to initiate the execution of each segment synchronously. The processors write to the same program variable, in a non volatile RAM (66, 76), only in alternate segments so that one processor, executing in an adjacent segment, forms a source of unaltered variable values for the other to use in recovering from a power interruption. A status register (36) provides segment completion status and a recovery table in a read only memory (62, 72) provides a list of variables that may be altered in each segment. After a power interruption the status register identifies the storage register to use for initial segment instruction addresses and the segment in the recovery table for variable identification. The processors may then obtain variable values from the non volatile RAM and recover segment execution. The system configuration also provides fault tolerance and self checking capabilities.

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