Source-coupled FET logic circuit
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United States of America Patent
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-
Jan 5, 1993
Grant Date -
N/A
app pub date -
May 7, 1991
filing date -
May 8, 1990
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A source-coupled FET logic (SCFL) circuit having a switching section and a source-follower section. The switching section receives two input signals, and out puts two signals, which are at complementary levels, to the source-follower section. The source-follower section comprises two FETs, two level-shifting circuits, a current source, and two capacitors. The first and second FETs receive at their gates the two signals output by the switching section, respectively. The first and second level-shifting circuits are connected to the sources of the first and second FETs, respectively. Either level-shifting circuit comprises n diodes connected in series. The two capacitors are connected in parallel to the first and second level-shifting circuits, respectively.
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