CMOS buffer circuit which is not influenced by bounce noise
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United States of America Patent
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Jan 12, 1993
Grant Date -
N/A
app pub date -
Jan 16, 1991
filing date -
Jan 17, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
This invention relates to an input buffer circuit including a NOT circuit composed of N-channel MOS transistor (NMOST) and P-channel MOS transistor (PMOST). This adjusts the resistance value between the NMOST and grounding voltage VSS, or the resistance value between the PMOST and supply voltage VCC, or both resistance values so as to decrease the current flowing the supply voltage VCC to the grounding voltage VSS. According to the construction, the power consumption is suppressed, and floating of grounding voltage VSS and lowering of supply voltage VCC may be prevented, so that the switching level of the input signal will not be deviated from the target value.
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