Importance

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Abstract

A bus access controller. An interface circuit (22) controls the access of a host computer (10) and a microprocessor (23) to one or more UARTs (14, 15). The microprocessor (23), which has no provision for waiting for a data transfer, is required to provide a signal of its intent to perform a data transfer prior to beginning the actual data transfer. The signal is identical to the actual data transfer operation. If the host (10) attempts a data transfer operation while the microprocessor (23) is conducting a data transfer operation, or if the host data transfer cannot be completed prior to the time that the microprocessor data transfer will commence, then the interface circuit (22) signals the host (10) that the data transfer will take additional time by deasserting the I/O READY line (12a). Once the microprocessor data transfer is completed then the I/O READY signal is reasserted and the host data transfer is completed. Bus contention problems and data loss are therefore prevented and the host (10) waiting time is minimized.

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First Claim