Tapered opening sidewall with multi-step etching process

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United States of America Patent

PATENT NO 5180689
SERIAL NO

07757135

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Abstract

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A method is described for making a tapered opening for an integrated circuit having a feature size of about one micrometer or less which will in due course be filled with a metallurgy conductor. An integrated circuit structure is provided having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the said multilayer insulating layer having openings therein in the areas where the said openings are desired. The multilayer insulating layer is anisotropically etched through a first thickness to form a first opening using the resist masking layer as a mask. A second thickness portion of the multilayer insulating layer is isotropically etched to substantially uniformly enlarge and taper the first opening while using the unchanged resist layer. The remaining thickness of the multilayer insulating layer is anisotropically etched through to the semiconductor substrate to form the desirable tapered opening with a metal step coverage improvement over the state of the art between about 20 to 60%. Metal step coverage is defined as the ratio of thickness of the thinnest metal in the contact hole to the metal thickness on the horizontal area. The resist layer mask is removed.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD629 EUCLID AVENUE SUITE 1000 CLEVELAND OH 44114

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Jin-Yuan Hsin-Chu, TW 318 8024
Liu, Hsien-Tsung Keelung, TW 7 80
Wang, Jiann-Kwang Hsin Chu, TW 5 460
Wang, Pei-Jan Taichung, TW 6 116
Yoo, Chue-San Taipei, TW 45 1145

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