Control of backgate bias for low power high speed CMOS/SOI devices
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United States of America Patent
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Feb 9, 1993
Grant Date -
N/A
app pub date -
Jun 17, 1991
filing date -
Jun 17, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N-silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.
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