Placement optimization system aided by CAD

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United States of America Patent

PATENT NO 5187668
SERIAL NO

07621893

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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There is provided a placement optimization system for determining layout in printed circuits and semiconductor substrates, comprising input means for inputting circuit connection information, placement optimization means for deriving wiring density distribution on the basis of the circuit connection information, evaluating the height and/or width of the wiring region statistically estimated from the wiring density distribution, and output means for outputting the resultant placement position information. Further, the placement optimization system may comprise means for collecting placement elements into sets, determining placement of the sets, then developing the sets into elements, and determining optimum placement positions of the elements.

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Patent Owner(s)

Patent OwnerAddress
MATSUSHITA ELECTRIC INDUSTRIAL CO LTD A CORP OF JAPAN1006 OAZA KADOMA KADOMA-SHI OSAKA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akino, Toshiro Takatsuki, JP 13 424
Okude, Hiroaki Takatsuki, JP 3 101
Toyonaga, Masahiko Takatsuki, JP 26 680

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