Triple self-aligned metallurgy for semiconductor devices
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 23, 1993
Issued Date -
N/A
app pub date -
Jun 3, 1992
filing date -
Jun 29, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully