US Patent No: 5,189,506

Number of patents in Portfolio can not be more than 2000

Triple self-aligned metallurgy for semiconductor devices

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Abstract

A process is described which eliminates the need to account for mask alignment tolerances in forming vias for metallurgy by the use of a common vertical edge or common plane defined by a first mask representing a first level of interconnect. Subsequent masks for defining interconnecting vias and a second level of interconnect utilize at least one edge of the first mask pattern as a common element to define subsequent metal levels. The combination of an etch stop layer and an oversized second level mask enable the mask overlay to be eliminated.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY68180

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cronin, John E Milton, VT 81 2679
Kaanta, Carter W Colchester, VT 23 1685

Cited Art

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
4,789,648 Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias 397 1985
 
KABUSHIKI KAISHA TOSHIBA (1)
4,582,563 Process for forming multi-layer interconnections 58 1984
 
U.S. PHILIPS CORPORATION (1)
4,892,843 Method of manufacturing a semiconductor device 16 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
ROUND ROCK RESEARCH, LLC (10)
6,414,392 Integrated circuit contact 7 2000
7,049,244 Method for enhancing silicon dioxide to silicon nitride selectivity 1 2001
7,282,440 Integrated circuit contact 1 2002
6,573,601 Integrated circuit contact 7 2002
7,315,082 Semiconductor device having integrated circuit contact 1 2003
7,569,485 Method for an integrated circuit contact 1 2004
7,282,447 Method for an integrated circuit contact 2 2004
7,276,448 Method for an integrated circuit contact 1 2004
7,871,934 Method for an integrated circuit contact 0 2007
8,097,514 Method for an integrated circuit contact 0 2009
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (4)
5,539,255 Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal 20 1995
5,663,101 Semiconductor structure having multiple levels of self-aligned interconnection metallization, and methods for its preparation 41 1996
6,121,129 Method of contact structure formation 12 1997
5,960,254 Methods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization 17 1997
 
ADVANCED MICRO DEVICES, INC. (3)
5,847,462 Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 4 1996
6,090,703 Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer 5 1998
6,127,264 Integrated circuit having conductors of enhanced cross-sectional area 5 1998
 
FREESCALE SEMICONDUCTOR, INC. (2)
6,143,648 Method for forming an integrated circuit 10 1997
6,372,638 Method for forming a conductive plug between conductive layers of an integrated circuit 4 2000
 
GLOBALFOUNDRIES INC. (2)
5,767,012 Method of forming a recessed interconnect structure 13 1996
6,031,289 Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines 4 1998
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (2)
5,668,412 Capacitor of a semiconductor device 7 1996
5,744,389 Method for fabricating a semiconductor device having a capacitor 5 1997
 
INTEGRATED DEVICE TECHNOLOGY, INC. (2)
5,471,094 Self-aligned via structure 5 1994
6,372,641 Method of forming self-aligned via structure 1 1996
 
CYPRESS SEMICONDUCTOR CORPORATION (1)
6,770,566 Methods of forming semiconductor structures, and articles and devices formed thereby 0 2002
 
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE (1)
5,891,799 Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates 116 1997
 
KABUSHIKI KAISHA TOSHIBA (1)
5,258,328 Method of forming multilayered wiring structure of semiconductor device 21 1993
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
5,858,578 Photo masks for developing planar layers in a semiconductor device, and methods of forming the same 1 1996
 
QIMONDA AG (1)
6,127,721 Soft passivation layer in semiconductor fabrication 3 1997
 
SGS-THOMSON MICROELECTRONICS, INC. (1)
5,309,025 Semiconductor bond pad structure and method 16 1992
 
UNITED MICROELECTRONICS CORP. (1)
5,596,230 Interconnection with self-aligned via plug 26 1996