Importance

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Abstract

A semiconductor memory device includes a memory cell including a volatile memory cell portion having a flip-flop and a non-volatile memory cell portion individually and respectively associated with the volatile memory cell portion and including a capacitor portion operatively connected to the volatile memory cell portion, a memory transistor operatively connected to the capacitor portion, and a recall transistor connected between the memory transistor and one of a pair of nodes of the flip-flop and selectively turned ON in a recall operation. The capacitor portion comprises a tunnel capacitor, used in a store operation, connected in series with a further capacitor and to which is applied a difference voltage between the respective voltages appearing at the pair of nodes. The space occupied by the memory cells on a chip is reduced and the degree of integration of the circuit is increased.

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First Claim