Importance

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Abstract

In an asynchronous transfer mode (ATM) switching system, an N-byte ATM cell containing a header and user data is received from a line circuit and an N-bit header containing routing information is derived from the received header. The received ATM cell is converted into a sequence of N parallel data bits and supplied to a first-stage controller to generate a first switching control signal. A successive bit of the N-bit header of the ATM cell is switched through a first-stage header-transfer switch in response to the first switching control signal and successive N parallel data bits of the cell are switched through a first-stage cell-transfer switch in response to the same control signal in synchronism with the first-stage header-transfer switch. A second-stage controller is responsive to the N-bit header switched from the first-stage header-transfer switch for generating a second switching control signal. A second-stage cell-transfer switch switches successive N parallel data bits of the ATM cell supplied from the first-stage cell-transfer switch in response to the second switching control signal. Successive N parallel data bits of the ATM cell supplied from the second-stage cell-transfer switch are converted to serial form for transmission to the next stage or switching system.

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