Method for producing a doped polycide layer on a semiconductor substrate

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5190888
SERIAL NO

07779408

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

Method for producing a doped polycide layer on a semiconductor substrate. A polycide layer (14) is formed by producing a metal silicide layer (13a) on a polysilicon layer (12a). After the formation thereof, the polycide layer (14) is doped to an ulltimate value of the dopant concentration by an implantation. The polysilicon layer can be pre-doped. The method is particularly suited for the manufacture of p.sup.+ -doped polycide gates in a salicide process.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
INFINEON TECHNOLOGIES AGMUNICH7467

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Burmester, Ralf Ratingen, DE 2 24
Schwalke, Udo Williston, VT 29 435

Cited Art Landscape

Patent Info (Count) # Cites Year
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
* 4912061 Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer 76 1988
 
SIEMENS AKTIENGESELLSCHAFT (2)
* 4740479 Method for the manufacture of cross-couplings between n-channel and p-channel CMOS field effect transistors of static write-read memories 24 1986
* 4782033 Process for producing CMOS having doped polysilicon gate by outdiffusion of boron from implanted silicide gate 24 1986
 
RPX CORPORATION (1)
* 4808548 Method of making bipolar and MOS devices on same integrated circuit substrate 44 1987
 
INTERSIL CORPORATION (1)
* 4933994 Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide 30 1988
 
TEXAS INSTRUMENTS INCORPORATED (2)
* 4816423 Bicmos process for forming shallow npn emitters and mosfet source/drains 27 1987
* 5059546 BICMOS process for forming shallow NPN emitters and mosfet source/drains 10 1989
 
BELL TELEPHONE LABORATORIES, INCORPORATED (1)
* 4555842 Method of fabricating VLSI CMOS devices having complementary threshold voltages 42 1984
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
* 5770490 Method for producing dual work function CMOS device 45 1996
* 6028339 Dual work function CMOS device 28 1998
 
TOSHIBA MEMORY CORPORATION (2)
* 6703669 Semiconductor device having serially connected memory cell transistors provided between two current terminals 15 2000
6828627 Semiconductor device 12 2003
 
TEXAS INSTRUMENTS-ACER INCORPORATED (1)
* 5956584 Method of making self-aligned silicide CMOS transistors 25 1998
 
SEIKO EPSON CORPORATION (2)
* 5879979 Method of manufacturing a semiconductor device containing CMOS elements 2 1995
* 6156592 Method of manufacturing a semiconductor device containing CMOS elements 1 1998
 
U.S. BANK NATIONAL ASSOCIATION (2)
* 6613654 Fabrication of semiconductor devices with transition metal boride films as diffusion barriers 5 2000
* 2003/0203,608 Fabrication of semiconductor devices with transition metal boride films as diffusion barriers 8 2003
 
MICRON TECHNOLOGY, INC. (3)
* 2002/0132,441 Suppression of cross diffusion and gate depletion 0 2001
6872639 Fabrication of semiconductor devices with transition metal boride films as diffusion barriers 25 2003
* 6962841 Suppression of cross diffusion and gate depletion 5 2003
 
University of Saskatchewan (2)
* 6953962 Nonvolatile memory device having a gate electrode 0 2005
* 2005/0127,430 Non volatile memory device having a gate electrode 0 2005
 
NORTH STAR INNOVATIONS INC. (2)
* 7179700 Semiconductor device with low resistance contacts 3 2004
* 2006/0017,110 Semiconductor device with low resistance contacts 0 2004
 
FUJI ELECTRIC CO., LTD. (1)
* 5618755 Method of manufacturing a polycide electrode 9 1995
 
LG Semicon Co., Ltd. (1)
* 6087246 Method for fabricating dual gate semiconductor device 4 1998
 
NATIONAL SEMICONDUCTOR CORPORATION (2)
* 5759886 Method for forming a layer of metal silicide over the gates of a surface-channel CMOS device 16 1996
* 7145191 P-channel field-effect transistor with reduced junction capacitance 29 2004
 
UNITED MICROELECTRONICS CORP. (1)
* 5416038 Method for producing semiconductor device with two different threshold voltages 14 1994
 
PS4 LUXCO S.A.R.L. (2)
* 6800543 Semiconductor device having a low-resistance gate electrode 12 2002
* 2003/0170,942 Semiconductor device having a low-resistance gate electrode 3 2002
 
LONGITUDE SEMICONDUCTOR S.A.R.L. (2)
* 7078777 Semiconductor device having a low-resistance gate electrode 0 2004
* 2005/0020,045 Semiconductor device having a low-resistance gate electrode 0 2004
 
PROMOS TECHNOLOGIES INC. (2)
* 6544888 Advanced contact integration scheme for deep-sub-150 nm devices 8 2001
* 2003/0003,640 Advanced contact integration scheme for deep-sub-150 NM devices 2 2001
 
NEC ELECTRONICS CORPORATION (1)
* 6232227 Method for making semiconductor device 13 2000
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
* 2007/0134,898 Semiconductor device manufacturing method 4 2006
 
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. (1)
* 6326252 Method for fabricating MOS transistor having dual gate 3 2000
 
MITSUMI ELECTRIC CO., LTD. (1)
* 6734075 CMOS device having high-density resistance elements 1 1999
* Cited By Examiner