Three-dimensional stacked LSI
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United States of America Patent
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-
Mar 2, 1993
Grant Date -
N/A
app pub date -
Dec 19, 1989
filing date -
Dec 23, 1988
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Disclosed is a three-dimensionally stacked LSI having a plurality of integrated-circuit layers stacked together, each of which is equipped with a plurality of circuit elements. Each of the circuit elements are equipped a power terminal of its own, which is connected through interlayer via-hole wiring to the power wiring of the uppermost integrated-circuit layer. The power wiring of the uppermost integrated-circuit layer is formed of a metal exhibiting a low electrical resistance, for example, Al, whereas the metal wirings of the other layers, which are exposed to high temperatures when forming the upper layers, are formed of W.
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