Method of fabricating field effect transistors
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United States of America Patent
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Mar 9, 1993
Grant Date -
N/A
app pub date -
Dec 17, 1990
filing date -
Dec 17, 1990
priority date (Note) -
Expired
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Abstract
Method of fabricating a junction field effect transistor employing self-alignment techniques. The active regions of the device are defined by a relatively thin thermally-grown isolating silicon oxide layer at the surface of a silicon body. After the active source and gate regions of the device as defined by the thermally-grown isolatign silicon oxide are formed in the silicon, a layer of deposited silicon oxide is formed over the thermally-grown silicon oxide. This method provides a thick dielectric layer as well as control of the horizontal dimensions of the source and gate contacts.
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