Digital phase locked loop circuit
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United States of America Patent
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-
Mar 9, 1993
Issued Date -
N/A
app pub date -
Jul 15, 1991
filing date -
Mar 2, 1988
priority date (Note) -
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status (Latency Note)
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Abstract
An all-digital phase locked loop circuit is described in which a numerically controlled oscillator is driven at a multiple of a required output frequency; a counter is provided to divide the output frequency of the oscillator by the multiple; an analogue to digital converter is provided to sample an input signal having the required frequency, and the frequency of the numerically controlled oscillator provides the sampling rate of the converter.
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