Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
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United States of America Patent
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Mar 9, 1993
Grant Date -
N/A
app pub date -
Jun 29, 1990
filing date -
Jun 29, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.
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