US Patent No: 5,193,193

Number of patents in Portfolio can not be more than 2000

Bus control system for arbitrating requests with predetermined on/off time limitations

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ATTORNEY / AGENT: (SPONSORED)
 

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Abstract

A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MORGAN STANLEY & CO., INCORPORATEDMOUNTAIN VIEW, CA707
SILICON GRAPHICS, INC.MOUNTAIN VIEW, CA506

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Iyer, Sanjay Stanford, CA 5 271

Cited Art

Patent Info (Count) # Cites Year
 
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ELEVATOR GMBH (1)
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INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
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MAXTOR CORPORATION (1)
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QUANTEL LIMITED (1)
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SAMSUNG ELECTRONICS CO., LTD. (1)
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SIEMENS AKTIENGESELLSCHAFT (1)
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SILICON GRAPHICS, INC. (1)
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SONY CORPORATION (1)
4,928,234 Data processor system and method 24 1988

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
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6,452,863 Method of operating a memory device having a variable data input length 38 2000
6,378,020 System having double data transfer rate and intergrated circuit therefor 46 2000
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6,751,696 Memory device having a programmable register 40 2001
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6,728,819 Synchronous memory device 8 2002
6,684,285 Synchronous integrated circuit device 10 2002
7,209,997 Controller device and method for operating same 2 2003
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (6)
5,590,372 VME bus transferring system broadcasting modifiers to multiple devices and the multiple devices simultaneously receiving data synchronously to the modifiers without acknowledging the modifiers 9 1992
5,524,270 System for transferring data between asynchronous data buses with a data buffer interposed in between the buses for synchronization of devices timed by different clocks 31 1993
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FREESCALE SEMICONDUCTOR, INC. (5)
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5,890,196 Method and apparatus for performing page mode accesses 4 1996
 
INTEL CORPORATION (5)
5,345,577 Dram refresh controller with improved bus arbitration scheme 25 1992
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5,682,498 Computer system with dual ported memory controller and concurrent memory refresh 14 1996
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MICRON TECHNOLOGY, INC. (3)
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CYPRESS SEMICONDUCTOR CORPORATION (2)
7,107,365 Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus 7 2002
7,275,119 Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus 1 2006
 
SONY COMPUTER ENTERTAINMENT INC. (2)
5,682,555 Bus control apparatus 3 1995
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TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (2)
5,301,332 Method and apparatus for a dynamic, timed-loop arbitration 39 1992
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ADVANCED MICRO DEVICES, INC. (1)
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APPLE INC. (1)
5,557,755 Method and system for improving bus utilization efficiency 4 1994
 
CANON KABUSHIKI KAISHA (1)
5,557,783 Arbitration device for arbitrating access requests from first and second processors having different first and second clocks 18 1994
 
DELL USA, L.P. (1)
5,517,671 System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus 11 1993
 
FUNK, STEVEN R. (1)
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HONEYWELL INC. (1)
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KABUSHIKI KAISHA TOSHIBA (1)
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MAXTOR CORPORATION (1)
5,771,397 SCSI disk drive disconnection/reconnection timing method for reducing bus utilization 3 1996
 
MICROUNITY SYSTEMS ENGINEERING, INC. (1)
5,630,096 Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order 50 1995
 
MITA INDUSTRIAL CO., LTD. (1)
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NEC INFRONTIA CORPORATION (1)
5,280,628 Interruption controlling system using timer circuits 8 1992
 
RENESAS ELECTRONICS AMERICA, INC. (1)
5,416,916 Structure for enabling direct memory-to-memory transfer with a fly-by DMA unit 12 1993
 
RENESAS ELECTRONICS CORPORATION (1)
5,467,454 Bus use request adjusting apparatus allowing changing priority levels 9 1993
 
SUN MICROSYSTEMS, INC. (1)
5,544,332 Method for preventing deadlock in a multi-bus computer system 23 1995
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,596,749 Arbitration request sequencer 10 1992
 
TOSHIBA STORAGE DEVICE CORPORATION (1)
6,324,120 Memory device having a variable data output length 41 2001
 
VISTEON GLOBAL TECHNOLOGIES, INC. (1)
6,473,821 Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems 9 1999
 
XEROX CORPORATION (1)
5,440,698 Arbitration of packet switched busses, including busses for shared memory multiprocessors 92 1994