Method for fabricating semiconductor circuits
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United States of America Patent
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Mar 23, 1993
Grant Date -
N/A
app pub date -
Jan 18, 1989
filing date -
Jan 18, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.
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