Sliced addressing multi-processor and method of operation
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United States of America Patent
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-
Mar 23, 1993
Grant Date -
N/A
app pub date -
Nov 17, 1989
filing date -
Nov 17, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.
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