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Abstract

Disclosed is a method of manufacturing a multilayer circuit board. The interlayer electrical connection between the lower-layer and upper-layer electric circuits is formed in the same photoresist step as the formation of the lower-layer electrical circuit. The process includes sequentially coating at least two metal layers onto the circuit board substrate, and therteafter applying positive photoresist on the upper metal layer of the metal layers. The photoresist is then imaged, i.e., exposed and developed, to define a predetermined pattern. The metal layers uncovered by the photolithopgraphy are etched, leaving a predetermined pattern. Then the upper metal layer not covered by the remaining photoresist is etched to form a via bump and the lower-layer electric circuit. In the next step the remaining photoresist on the upper metal layer is removed, an organic dielectric layer on said etched metal layers, the surface of the organic dielectric layer is flattened to expose the surface of the via bump, and another metal layer is deposited atop the dielectric. This layer constitutes the upper-layer electric circuit atop the organic dielectric layer and the exposed surfaces of the via bump.

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First Claim