Lateral type semiconductor device having a structure for eliminating turning-on of parasitic MOS transistors formed therein

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5204543
SERIAL NO

07918117

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A semiconductor device comprises a substrate of a first conduction type defined by a major surface, a pair of conductive regions of a second conduction type formed in the substrate along the major surface, an intervening region of the first conduction type formed in the substrate between the pair of conductive regions so as to separate the pair of conductive regions from each other, a first insulator film provided on the substrate so as to cover the major surface thereof including the pair of conductive regions and the intervening region located therebetween, a first conductor layer provided so as to extend generally parallel to the major surface of the substrate with a separation from the first insulator film, the first conductor layer crossing a part of the intervening region at a level separated therefrom, a second conductor layer provided on the first insulator film at a level below the first conductor layer so as to cover at least the part of the intervening region which is crossed by the first conductor layer, a second insulator film interposed between the second conductor layer and the first conductor layer, and a circuit for applying a predetermined voltage to the second conductor layer, the predetermined voltage having a magnitude chosen such that turning-on of a parasitic MOS transistor formed in the semiconductor device is eliminated.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • FUJITSU MICROELECTRONICS LIMITED;FUJITSU VLSI LIMITED

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujimura, Yukinori Owariasahi, JP 1 2
Hanazawa, Toshio Kasugai, JP 11 100
Matsumoto, Takashi Inazawa, JP 564 7219

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation