Importance

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Abstract

A first-in, first-out (FIFO) memory includes flag generation circuitry which utilizes a write clock counter and a read clock counter to provide the number of write clock pulses received since the previous write reset signal and the number of read clock pulses received by the FIFO since the previous read reset signal. Specific flag values are user-programmable and are stored electronically as binary numbers in registers. The connection between individual subtractor circuits and individual comparator circuits for making a difference comparison is performed by a program select decoder which utilizes the difference output of the subtractor circuit and the flag program value. False flag information is filtered by a bi-stable de-glitch circuit which includes a delay path to emulate operation of the counter, subtractor and comparator. The magnitude comparator is programmed one count away from the desired flag transition point. The filtered flag output is updated at the onset of each blanking interval, thus making it representative of the current state of the FIFO.

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First Claim