Importance

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Abstract

An accumulation circuit includes an adder circuit, the output of which is stored in an accumulator (a register). A selection circuit is also provided which selectively outputs the output of the accumulator or a predetermined initial value to one of input terminals of the adder. A shifter is provided to shift bit positions of the output data of the accumulator by a predetermined number of bit positions for a rounding-off operation. Another one of the input terminals of the adder circuit is input with data to be accumulated. On beginning a new accumulation operation, the selection circuit is instructed by an initializing signal so as to select the initial value. When the round-off is not necessary, the initial value is set zero. For round-off operation, the initial value is generated by a decoder depending on a shift number output from a shift-number register, so that the initial value has a bit 1 located in 1/2 LSB (least significant bit) position of the rounded-off datum by the shifter as well as bits zero located in all other bit positions than the 1/2 LSB position. The circuit configuration allows to delete an extra clock cycle exclusively needed for the initializing, so as to enhance the accumulation speed, and a round-off circuit independently required in a prior art circuit configuration.

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First Claim