Clock signal multiplier
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United States of America Patent
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-
May 4, 1993
Grant Date -
N/A
app pub date -
Mar 30, 1990
filing date -
Mar 30, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.
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