Selective plating method for forming integral via and wiring layers

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5209817
SERIAL NO

07748445

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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In a multi-level wiring structure wires and vias are formed by an isotropic deposition of a conductive material, such as copper, on a dielectric base, such as a polyimide. In a preferred embodiment of the invention copper is electroplated to a thin seed conducting layer deposited on the surface of the dielectric base in which via openings have been formed. Openings in a resist formed on the surface of the dielectric base over the seed layer forms a pattern defining the wiring and via conductor features. Electroplated copper fills the via openings and wire pattern openings in the resist isotropically so that the upper surfaces of the wiring and vias are co-planar when the plating step is complete. In adding subsequent wiring levels, the resist is removed and the via conductor and wiring pattern covered with another dielectric layer which both encapsulates the conductors of the previous layer and serves as the base for the next level which is formed in the same manner as the previous level.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATION A CORP OF NEW YORKARMONK NY 10504

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ahmad, Umar M Hopewell Junction, NY 11 630
Berger, Daniel G Poughkeepsie, NY 12 420
Kumar, Ananda Hopewell Junction, NY 14 846
LaMaire, Susan J Yorktown Heights, NY 3 235
Prasad, Keshav B New Paltz, NY 2 229
Ray, Sudipta K Wappingers Falls, NY 42 1526
Wong, Kwong H Croton-On-Hudson, NY 13 871

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