Configuration of SRAMS as logical FIFOS for transmit and receive of packet data
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United States of America Patent
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May 11, 1993
Grant Date -
N/A
app pub date -
May 29, 1990
filing date -
May 29, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Data arranged in packets are transferred between a system memory and a network bus through a SRAM configured by software pointers as first in-first out memories for transmitting (transmit FIFO) and for receiving (receive FIFO). The packets of data stored in the transmit and receive FIFOs are demarked from each other and classified by tag and status bits at the end of the last word of each packet. Data to be transmitted on the network bus is transferred from the system memory to the transmit FIFO, and data received from the network is stored in the receive FIFO. To maximize data throughput, when either at least a predetermined amount of data or a complete packet is stored in the transmit FIFO, the data is transmitted to the network while data is being received from the system memory. When at least a predetermined amount of data is stored in the receive FIFO, data is transferred to the system memory while network data is incoming from the network. One application of the invention is in a Fiber Distributed Data Interface (FDDI).
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| GLOBALFOUNDRIES INC | MAPLES CORPORATE SERVICES LIMITED PO BOX 309 UGLAND HOUSE GRAND CAYMAN KY1-1104 |
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Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Firoozmand, Farzin | Cupertino, CA | 6 | 486 |
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