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Abstract

An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.

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First Claim