Importance

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Abstract

A memory device having a fast access, or cache, mode is disclosed. The memory has an address transition detection circuit for detecting a transition in a portion of the memory address presented to the memory, for example the row address. The memory is operable to select a previously sensed memory cell responsive to the remainder of the address without requiring a transition in the first portion of the address, and without requiring the precharge portion of the memory cycle. For example, the column address selects a bit to be communicated from the sense amplifiers, which are retaining the previously sensed data. The sense amplifiers retain the previously sensed data for so long as no transition in the row address occurs; the memory may include a terminal for receiving a signal which disables the effect of an address transition, so that the fast access mode is retained without regard to transitions in the row address portion of the memory address. A second embodiment having the fast access mode also has its array organized into blocks, so that the sense amplifiers for each array block can store data from a memory row different from those stored in the sense amplifiers for other blocks, allowing for an improved cache hit rate.

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First Claim