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Abstract

The switching element is used for transferring, between X inputs (I1-IX) and Y outputs (O1-OY), cells divided into subcells of which only the first contains information about the destination output(s) of the cell. This switching element includes: a buffer memory (BM) with a plurality (C) of memory locations each having an address (K); and a memory management means (BMMU) for providing (FMLMC) addresses of free memory locations for storing the subcells therein, and for storing (BQ1-BQY, SLM), under the form of linked lists, the memory location addresses used by the subcells, each list being associated to a distinct cell. The method is adapted to process variable length cells divided into subcells each containing a header (SCH) to distinguish a first/last subcell (FSC/LSC) of a cell from other subcells (ISC, LSC). Use is made of a subcell logic (SL) to detect the succession in either order of a subcell pertaining to a cell and of either a first/last subcell (FSC/LSC) of another cell or an idle subcell so as to identify the last/first subcell (LSC/FSC) of a cell.

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