Importance

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Abstract

Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any successfully-completed instructions and without any abnormal ending being provided to the program. The continued program need not have any built-in recovery or correction code. Predetermined register contents in the failed processor are stored in predetermined storage locations by the the failing processor or by a service processor (SP) when the failing processor has not been able to store this information. The predetermined contents saved from the failed processor are defined by the system architecture for saving an interruption of a program to enable the continuation of execution of the program after restoring the contents of PSWs, CRs, FPRs, GPRs, ARs, etc. if using the ESA/370 architecture. When a failed processor is detected, the SP issues an external interruption to other processors in the system that are operable for continuing the execution of the failed processor task after the required information is stored. Special indicators are stored in predetermined places in the system and/or microcode memory that is accessible to the SP and to the healthy processors in the system selectable for continuing the task' s execution.

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First Claim