Electro-optical method and apparatus for testing integrated circuits
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United States of America Patent
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Jun 1, 1993
Grant Date -
N/A
app pub date -
Jan 18, 1991
filing date -
Jan 18, 1991
priority date (Note) -
Expired
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Abstract
Internal test sites on integrated circuit chips may be tested with minimal input/output pad or chip area overhead by providing transient interconnections to the internal test sites using an optically activated photoconductive layer which is formed over the active device layers of the integrated circuit to be tested. The photoconductive layer may be optically activated using an optical mask or hologram, to electrically access the desired internal test sites. Different test sites may be tested using different masks or holograms. The photoconductive layer is preferably hydrogenated amorphous silicon which is highly compatible with standard integrated circuit processing.
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