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Abstract

A 'single-chip' integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes. Synchronous units which handle data are configured to form plural stage pipelines, in each direction of communication, which eases timing requirements at the bus interface. Status information is stored queued in memory unit storage spaces dedicated to the channels; each queue configured so that the system CPU can retrieve status information representing plural events in one channel in one coherent bus operation. The device is partitioned further to provide discretely separate internal paths for transferring service and data signals relative to the system. Service signal transfers to and from system CPU and directed by the CPU. Data signal transfers to and from system memory are directed by a DMA control unit in the device.

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First Claim