Importance

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Abstract

During the manufacture of a semiconductor integrated circuit, contact holes or passages are formed through a non-planar insulating layer resulting from the deposition of dielectric over electrical contacts having differing profile heights from the surface of an internal layer, such as a substrate, to expose these contacts and/or provide electrical connections thereto. The passages are formed with a combination of sloped and vertical sidewall portions in which varying depth sloped portions are used to effectively planarize the dielectric layer and permit the vertical sidewall portions to have substantially identical vertical dimensions. This technique simultaneously exposes contacts with varying profile heights which thereby reduces contact damage. In addition, this technique effectively planarizes the dielectric layer, reducing the need for an additional planarization step.

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First Claim