Importance

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Abstract

A Delay Locked Loop For Clock Synchronization is disclosed that solves the problem of aligning a clock signal (V.sub.OUT) with a reference signal (REF) in the shortest time and without instability. The clock signal (V.sub.OUT) is passed through an conventional, variable delay line (20) whose phase delay is controlled by a charge (V.sub.CTRL) on a capacitor (C). The invention employs an improved phase detection system (21) including first and second phase detectors (22), (26) and a first logic gate (28). The reference signal (REF) is delayed at the second phase detector (26). A logic circuit (30) is reset by a pulse (nReset) charging the capacitor (C) to a maximum voltage (V.sub.CTRL). Maximum voltage (V.sub.CTRL) drives the variable delay line (20) to the minimum achievable delay. The reset pulse (nReset) is then removed, and the voltage (V.sub.CTRL) is bled from the capacitor (C), increasing the phase delay between the clock signal (V.sub.OUT) and the reference signal (REF). When the clock signal (V.sub.OUT) has been delayed sufficiently that the first and second phase detectors (22), (26) agree that more phase delay will bring the clock signal (V.sub.OUT) into alignment with the reference signal (REF), the set-reset circuit (32) is set. This enables the complimentary output (nQ) of the first phase detector (22) to regulate the voltage (V.sub.CTRL) on the capacitor (C), adjusting the variable delay line (20) to bring the clock signal (V.sub.OUT) into alignment with the reference signal (REF).

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First Claim