US Patent No: 5,224,056

Number of patents in Portfolio can not be more than 2000

Logic placement using positionally asymmetrical partitioning algorithm

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Abstract

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A modified partitioning method for placement of a circuit design into a programmable integrated circuit device (PICD), the PICD having a specific distribution of physical resources corresponding to a specific circuit structure. The circuit design includes a plurality of circuit elements which include specific circuit elements which correspond to the specific circuit structure. The modified method includes the steps of identifying the specific circuit elements and partitioning the plurality of circuit elements such that the identified specific circuit elements are placed in a location corresponding to the specific physical distribution of resources. In one embodiment of the modified partitioning method according to the present invention, the step of partitioning further includes the steps of forming into a cell the identified specific circuit elements and performing a first phase of partitioning wherein the cell and the remaining ones of the plurality of circuit elements are partitioned into successively smaller groups until a stop condition is satisfied. The cell is then decomposed such that the contents of the group containing the cell change to include the specific circuit elements. The group containing the specific circuit elements is then partitioned such that the area and the location of the group corresponds to the specific physical distribution of resources.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
XILINX, INC.SAN JOSE, CA3312

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chene, Mon R Cupertino, CA 1 125
Trimberger, Stephen M San Jose, CA 227 8856

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
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