
US Patent No: 5,224,056
Number of patents in Portfolio can not be more than 2000
Logic placement using positionally asymmetrical partitioning algorithm
Stats
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Jun 29, 1993
Issued date -
Oct 30, 1991
filing date -
07/784,844
serial no -
In Force
status

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Abstract
A modified partitioning method for placement of a circuit design into a programmable integrated circuit device (PICD), the PICD having a specific distribution of physical resources corresponding to a specific circuit structure. The circuit design includes a plurality of circuit elements which include specific circuit elements which correspond to the specific circuit structure. The modified method includes the steps of identifying the specific circuit elements and partitioning the plurality of circuit elements such that the identified specific circuit elements are placed in a location corresponding to the specific physical distribution of resources. In one embodiment of the modified partitioning method according to the present invention, the step of partitioning further includes the steps of forming into a cell the identified specific circuit elements and performing a first phase of partitioning wherein the cell and the remaining ones of the plurality of circuit elements are partitioned into successively smaller groups until a stop condition is satisfied. The cell is then decomposed such that the contents of the group containing the cell change to include the specific circuit elements. The group containing the specific circuit elements is then partitioned such that the area and the location of the group corresponds to the specific physical distribution of resources.
First Claim
Related Publications
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | Total Patents |
|---|---|---|
| XILINX, INC. | SAN JOSE, CA | 3059 |
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Chene, Mon R | Cupertino, CA | 1 | 124 |
| Trimberger, Stephen M | San Jose, CA | 210 | 7487 |
Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 4,890,238 Method for physical VLSI-chip design | 76 | 1987 | |
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| 4,967,367 Synthetic netlist system and method | 82 | 1988 | |
Patent Citation Ranking
Forward Cites
| Patent Info | (Count) | # Cites | Year |
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| 6,493,658 Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms | 33 | 1994 | |
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| 5,557,533 Cell placement alteration apparatus for integrated circuit chip physical design automation system | 83 | 1994 | |
| 5,495,419 Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing | 120 | 1994 | |
| 5,638,288 Separable cells having wiring channels for routing signals between surrounding cells | 11 | 1994 | |
| 5,587,923 Method for estimating routability and congestion in a cell placement for integrated circuit chip | 93 | 1994 | |
| 5,568,636 Method and system for improving a placement of cells using energetic placement with alternating contraction and expansion operations | 62 | 1994 | |
| 5,682,321 Cell placement method for microelectronic integrated circuit combining clustering, cluster placement and de-clustering | 28 | 1994 | |
| 5,781,439 Method for producing integrated circuit chip having optimized cell placement | 12 | 1995 | |
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| 6,030,110 Advanced modular cell placement system with median control and increase in resolution | 5 | 1996 | |
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| 5,963,455 Advanced modular cell placement system with functional sieve optimization technique | 6 | 1996 | |
| 5,914,888 Advanced modular cell placement system with coarse overflow remover | 3 | 1996 | |
| 5,892,688 Advanced modular cell placement system with iterative one dimensional preplacement optimization | 9 | 1996 | |
| 5,872,718 Advanced modular cell placement system | 4 | 1996 | |
| 5,870,311 Advanced modular cell placement system with fast procedure for finding a levelizing cut point | 0 | 1996 | |
| 5,870,312 Advanced modular cell placement system with dispersion-driven levelizing system | 8 | 1996 | |
| 5,867,398 Advanced modular cell placement system with density driven capacity penalty system | 6 | 1996 | |
| 5,844,811 Advanced modular cell placement system with universal affinity driven discrete placement optimization | 6 | 1996 | |
| 5,835,381 Advanced modular cell placement system with minimizing maximal cut driven affinity system | 2 | 1996 | |
| 5,831,863 Advanced modular cell placement system with wire length driven affinity system | 15 | 1996 | |
| 5,812,740 Advanced modular cell placement system with neighborhood system driven optimization | 6 | 1996 | |
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| 6,067,409 Advanced modular cell placement system | 108 | 1997 | |
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| 5,550,839 Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays | 85 | 1993 | |
| 5,513,124 Logic placement using positionally asymmetrical partitioning method | 60 | 1993 | |
| 5,521,837 Timing driven method for laying out a user's circuit onto a programmable integrated circuit device | 158 | 1995 | |
| 5,659,484 Frequency driven layout and method for field programmable gate arrays | 207 | 1995 | |
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| 7,382,156 Method and apparatus for universal program controlled bus architecture | 25 | 2005 | |
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| 7,646,218 Architecture and interconnect scheme for programmable logic circuits | 1 | 2008 | |
| 7,830,173 Method and apparatus for universal program controlled bus architecture | 2 | 2009 | |
| 7,915,918 Method and apparatus for universal program controlled bus architecture | 0 | 2010 | |
| 8,289,047 Architecture and interconnect scheme for programmable logic circuits | 0 | 2010 | |
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| 6,212,668 Gain matrix for hierarchical circuit partitioning | 8 | 1997 | |
| 6,301,694 Hierarchical circuit partitioning using sliding windows | 9 | 1997 | |
| 6,045,252 Methods for allocating circuit design portions among physical circuit portions | 4 | 1998 | |
| 7,318,210 Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays | 3 | 2006 | |
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| 5,398,195 Method and system for providing a non-rectangular floor plan | 53 | 1992 | |
| 5,648,912 Interconnection resource assignment method for differential current switch nets | 9 | 1993 | |
| 5,535,134 Object placement aid | 43 | 1994 | |
| 5,675,500 Multi-chip device partitioning process | 2 | 1994 | |
| 5,740,067 Method for clock skew cost calculation | 15 | 1995 | |
| 5,745,735 Localized simulated annealing | 32 | 1995 | |
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| 6,014,509 Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells | 106 | 1997 | |
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| 6,421,251 Array board interconnect system and method | 26 | 1998 | |
| 6,134,516 Simulation server system and method | 84 | 1998 | |
| 6,026,230 Memory simulation system and method | 72 | 1998 | |
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Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |