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Abstract

An arrangement method for logic cells in a semiconductor IC device, in which a plurality of logic cells are arranged on a semiconductor chip and wiring is performed between the logic cells so as to realize a desired circuit, comprises the steps of developing the logic cell informations to be arranged on the chip and already-arranged cell and wiring informations into connection pins and inhibited areas for wiring, converting the inhibited areas for wiring into equivalent pins so as to treat the inhibited areas for wiring equivalently with respect to the connection pins, and imaginarily dividing the chip into lattices and subsequently uniforming a ratio of a sum of the numbers of the connection pins and the equivalent pins to a region capable of arrangement in each lattice, whereby a position of each logic cell is determined.

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First Claim