Routing technique for a hierarchical interprocessor-communication network between massively-parallel processors
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United States of America Patent
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Jun 29, 1993
Grant Date -
N/A
app pub date -
May 9, 1991
filing date -
May 9, 1991
priority date (Note) -
Expired
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Abstract
A routing process for a single-instruction-multiple-data (SIMD) multi-level hierarchical network of nodes, which are arranged in clusters and interconnected by dual, unidirectional channels, are used to send data packets including routing address information during a succession of routing cycles from transmitting ones to receiving ones of a large number of parallel processors (e.g., 4096 processors arranged in a hierarchy of 8 cabinets, each of which contains a cluster of 8 circuit boards, with each circuit board containing a cluster of 64 processors). Each of the nodes includes a storage buffer having a capacity equal to a given number which is one more than the total number of channels terminating at that node. This routing process guarantees prevention of deadlock between levels and buffer overflow, and offers high-speed, low-cost interprocessor communication for SIMD computers.
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