Importance

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Abstract

A buffer memory circuit has a memory circuit for receiving input data possessing a transmission rate selected out of a plurality of predetermined transmission rates, a write-in clock signal synchronized with these input data and a read-out clock signal having a predetermined rate. The memory circuit stores the input data according to the write-in clock signal, and supplies the input data, which have been stored, as output data according to the read-out clock signal. A detecting circuit detects an overflow or an underflow in the memory circuit, and supplies a resetting pulse signal for initializing the memory circuit. A control circuit receives the write-in clock signal and the resetting pulse, and suspends the supply of the read-out clock signal to the memory circuit means for a certain period of time, determined by the first transfer rate, from the time of receiving the resetting pulse signal.

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First Claim