Program counter and indirect address calculation system which concurrently performs updating of a program counter and generation of an effective address
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United States of America Patent
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-
Jul 6, 1993
Issued Date -
N/A
app pub date -
Sep 4, 1991
filing date -
Oct 30, 1986
priority date (Note) -
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status (Latency Note)
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Abstract
A processor capable of processing a variable word length instruction has a program counter controlled to indicate the head of an instruction by the value of the program counter. There are provided an adder for summing the length of decoded portions in the variable word length instruction in accordance with the progress of the instruction decoding, and another adder for adding the length of the decoded instruction portions to the program counter so as to update the program counter. Further, there is provided a circuit for calculating an operand effective address by using the value of the program counter in the course of the variable word length instruction decoding. Thus, the updating of the program counter and the generation of the effective address are concurrently executed.
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