Semiconductor memory device with a built-in cache memory and operating method thereof
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United States of America Patent
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Jul 6, 1993
Grant Date -
N/A
app pub date -
Jan 8, 1991
filing date -
Jan 16, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed
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